Integrated circuits have progressed to advanced technologies with smaller feature sizes, such as 32 nm, 28 nm and 20 nm. In these advanced technologies, three dimensional transistors each having a multi-fin structure are often desired for enhanced device performance. However, existing methods and structures for such structures have various concerns and disadvantages associated with device quality and reliability. For example, fin height is defined by oxide recess. Therefore the fin height control will strongly depend on the factors including oxide quality, etch stability and fin bottom oxide shape. In another example, shallow trench isolation (STI) deposition/anneal will induce a stress, resulting in the fin distortion. This is the tradeoff between oxide quality and fin distortion ratio. In yet another example, the fin profile is defined by one etch step. It is challenging to have well control on fin profile and easily results in a taper fin shape (80˜87 degree) since the fin etch needs to cover different requirements including top shape and bottom shape.
Therefore, there is a need for a structure and method for a multi-fin device to address these concerns for enhanced performance and reduced fabrication cost.